SIMD128 LANE_ARCHITECTURE
VECTOR_REGISTER_f32x4
SIMD128 processes 4 float32 values simultaneously using a single 128-bit register.
Lane 0
f32
Lane 1
f32
Lane 2
f32
Lane 3
f32
EdgeVec uses f32x4.mul, f32x4.add, and horizontal sum for dot product calculations
RUN_BENCHMARK
BENCHMARK_CONFIG
0%
--
Total Ops
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Est. Time
BENCHMARK_RESULTS
--
Avg Latency (ns)
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Throughput (Gelem/s)
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Total Time (ms)
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Ops/sec
LATENCY_DISTRIBUTION
BROWSER_COMPATIBILITY
Chrome
91+
Firefox
89+
Edge
91+
Safari
16.4+ (macOS)
iOS Safari
All versions
BENCHMARK_LOG
[00:00:00]
EdgeVec SIMD Benchmark initialized. Click RUN_BENCHMARK to start.